As referred to as a memory wall problem, memory access is a bottleneck in performance and power consumption of processor cores. As a measure against the memory wall problem, there is a tendency for cache memories to have a larger capacity, along with which there is a problem of increase in leakage current of the cache memories.
MRAMs that attract attention as a candidate for a large-capacity cache memory are a non-volatile memory, having a feature of much smaller leakage current than SRAMs currently used in cache memories.
However, the MRAMs have a problem of a higher frequency of occurrence of bit errors than the SRAMs. Therefore, the MRAMs require an ECC (Error Check and Correction) circuitry. An error correction process by the ECC circuitry and memory access have to be performed one after another, which causes increase in latency of memory access.
The ECC circuitry generates a redundant code for each of cache lines of a cache memory which is accessed per cache line. Therefore, as the bit length of each cache line becomes longer, the time required for error correction becomes longer.